Verification Methodology Manual For Systemverilog: For Systemverilog
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- Format:
- Hardback
- Pages:
- 524
- Publisher:
- Springer-Verlag New York Inc.
- Publication Date:
- 01 September 2005
- Category:
- Systems Analysis & Design
- ISBN:
- 9780387255385
Description
Offers users the first resource guide that combines both the methodology and basics of SystemVerilog Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly. Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.
Also by Eduard Cerny, Alan Hunter and Janick Bergeron
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