Verification and Validation in Systems Engineering : Assessing UML/SysML Design Models Hardback
At the dawn of the 21st century and the information age, communication and c- puting power are becoming ever increasingly available, virtually pervading almost every aspect of modern socio-economical interactions.
Consequently, the potential for realizing a signi?cantly greater number of technology-mediated activities has emerged.
Indeed, many of our modern activity ?elds are heavily dependant upon various underlying systems and software-intensive platforms.
Such technologies are commonly used in everyday activities such as commuting, traf?c control and m- agement, mobile computing, navigation, mobile communication.
Thus, the correct function of the forenamed computing systems becomes a major concern.
This is all the more important since, in spite of the numerous updates, patches and ?rmware revisions being constantly issued, newly discovered logical bugs in a wide range of modern software platforms (e. g. , operating systems) and software-intensive systems (e. g. , embedded systems) are just as frequently being reported.
In addition, many of today's products and services are presently being deployed in a highly competitive environment wherein a product or service is succeeding in most of the cases thanks to its quality to price ratio for a given set of features.
Accordingly, a number of critical aspects have to be considered, such as the ab- ity to pack as many features as needed in a given product or service while c- currently maintaining high quality, reasonable price, and short time -to- market.
- Format: Hardback
- Pages: 248 pages, XXVI, 248 p.
- Publisher: Springer-Verlag Berlin and Heidelberg GmbH & Co. K
- Publication Date: 18/11/2010
- Category: Software testing & verification
- ISBN: 9783642152276