Please note: In order to keep Hive up to date and provide users with the best features, we are no longer able to fully support Internet Explorer. The site is still available to you, however some sections of the site may appear broken. We would encourage you to move to a more modern browser like Firefox, Edge or Chrome in order to experience the site fully.

Low-power High-level Synthesis for Nanoscale CMOS Circuits, Hardback Book

Low-power High-level Synthesis for Nanoscale CMOS Circuits Hardback

Hardback

Description

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies.  The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits.

The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level.  At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation. The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers.

Each chapter has simple relevant examples for a better grasp of the principles presented.

Several algorithms are given to provide a better understanding of the underlying concepts.

The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation.

In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including: • Power Reduction Fundamentals• Energy or Average Power Reduction• Peak Power Reduction• Transient Power Reduction• Leakage Power ReductionLow-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.

Information

  • Format:Hardback
  • Pages:302 pages, 25 Tables, black and white; 20 Illustrations, black and white; XXXII, 302 p. 20 illus.
  • Publisher:Springer-Verlag New York Inc.
  • Publication Date:
  • Category:
  • ISBN:9780387764733

Other Formats

Save 13%

£159.99

£137.89

Item not Available
 
Free Home Delivery

on all orders

 
Pick up orders

from local bookshops

Information

  • Format:Hardback
  • Pages:302 pages, 25 Tables, black and white; 20 Illustrations, black and white; XXXII, 302 p. 20 illus.
  • Publisher:Springer-Verlag New York Inc.
  • Publication Date:
  • Category:
  • ISBN:9780387764733