Please note: In order to keep Hive up to date and provide users with the best features, we are no longer able to fully support Internet Explorer. The site is still available to you, however some sections of the site may appear broken. We would encourage you to move to a more modern browser like Firefox, Edge or Chrome in order to experience the site fully.

Supporting your high street Find out how »
Wafer-Level Testing and Test During Burn-In for Integrated Circuits, PDF eBook

Wafer-Level Testing and Test During Burn-In for Integrated Circuits PDF

PDF

Download - Immediately Available
Please note: eBooks can only be purchased with a UK issued credit card and all our eBooks (ePub and PDF) are DRM protected.

Description

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form.

Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures.

This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.

Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints.

Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers.

Practitioners also find expert insights on current industry trends in WLTBI test solutions.

Information

Other Formats

Save 20%

£75.00

£60.00

Download - Immediately Available
Add to Basket
Sign in to add to wishlist
 
Delivered to your inbox

to transfer to your device

eBook Help

Is this the right eBook for
my device? How do I download
this eBook? See help and FAQs pages

Information