Please note: In order to keep Hive up to date and provide users with the best features, we are no longer able to fully support Internet Explorer. The site is still available to you, however some sections of the site may appear broken. We would encourage you to move to a more modern browser like Firefox, Edge or Chrome in order to experience the site fully.

Asynchronous System-on-Chip Interconnect, Paperback / softback Book

Asynchronous System-on-Chip Interconnect Paperback / softback

Part of the Distinguished Dissertations series

Paperback / softback

Description

Asynchronous System-on-Chip Interconnect describes the use of an entirely asynchronous system-bus for the modular construction of integrated circuits.

Industry is just awakening to the benefits of asynchronous design in avoiding the problems of clock-skew and multiple clock-domains, an din parallel with this is coming to grips with Intellectual Property (IP) based design flows which emphasise the need for a flexible interconnect strategy.

In this book, John Bainbridge investigates the design of an asynchronous on-chip interconnect, looking at all the stages of the design from the choice of wiring layout, through asynchronous signalling protocols to the higher level problems involved in supporting split transactions.

The MARBLE bus (the first asynchronous SoC bus) used in a commercial demonstrator chip containing a mixture of asynchronous and synchronous macrocells is used as a concrete example throughout the book.

Information

Other Formats

Save 17%

£76.50

£63.09

Item not Available
 
Free Home Delivery

on all orders

 
Pick up orders

from local bookshops

Information